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-- Company: 
-- Engineer:
--
-- Create Date:   17:28:45 11/28/2010
-- Design Name:   
-- Module Name:   E:/Dev/VHDL/copro/tb_sp_reg.vhd
-- Project Name:  copro
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: sp_reg
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY tb_sp_reg IS
END tb_sp_reg;
 
ARCHITECTURE behavior OF tb_sp_reg IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT sp_reg
    PORT(
         clk : IN  std_logic;
         reset : IN  std_logic;
         we : IN  std_logic;
         serial_in : IN  std_logic;
         parallel_out : OUT  std_logic_vector(31 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '1';
   signal we : std_logic := '1';
   signal serial_in : std_logic := '0';

 	--Outputs
   signal parallel_out : std_logic_vector(31 downto 0);

   -- Clock period definitions
   constant clk_period : time := 1us;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: sp_reg PORT MAP (
          clk => clk,
          reset => reset,
          we => we,
          serial_in => serial_in,
          parallel_out => parallel_out
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 2.5*clk_period.
      wait for clk_period*2.5;
	reset <= '0';
      wait for clk_period*10;

      -- insert stimulus here 
	serial_in <= '1';
		wait for clk_period*23;
	we <= '0';
		wait for clk_period*1.5;
	we <= '1';
      wait;
   end process;

END;
